targets/decklink_mini_4k: Generate exact video clocks - #764

Summary

• Generate the 148.5MHz system/video and 594MHz DDR3 clocks from the board's 24MHz clock-capable input with an S7 MMCM.
• Generate exact 200MHz IDELAY and 150MHz SATA reference clocks from the 100MHz input with one auxiliary PLL.
• Replace stale hard-coded clock-net constraints with a constraint resolved from the generated PLL input signal.
• Declare the independent 24MHz and 100MHz clock trees asynchronous.

Problem

The previous CRG requested 148.5MHz, 594MHz and 200MHz outputs from one integer S7 PLL driven at 100MHz. That combination cannot produce the required clocks exactly, so Vivado selected:

Besides moving the HDMI timing away from the requested 1080p60 mode, the 196.667MHz IDELAY clock did not match the IDELAYE2 200MHz reference-frequency setting.

The 24MHz input permits an exact MMCM configuration with a 49.5 multiplier and output dividers of 8 and 2. The 100MHz input permits exact 200MHz and 150MHz auxiliary PLL outputs.

Validation

• Default target generation with --build --no-compile.
• Framebuffer target generation with --with-video-framebuffer --build --no-compile.
• Vivado 2025.2 synthesis, placement and routing without bitstream generation.
• Final setup WNS: +0.170ns.
• Final hold WHS: +0.065ns.
• No unrouted nets, implementation errors, critical warnings, or IDELAY reference-frequency mismatch.

Hardware validation of the HDMI output is still requested in #763.

Related to #763.